A finFET refers to a fin-type field effect transistor. More specifically, a finFET includes at least a “fin” of semiconductor material formed on a substrate such that the fin sidewall planes are orthogonal to the plane of the substrate, a gate electrode disposed on the substrate and extending over and generally perpendicular to the at least one fin, and a source drain region one either side of the gate electrode. The at least one fins typically extend from under the gate into both source drain regions.
The performance of a finFET and other structures based on silicon-on-insulator (SOI) or extremely thin silicon-on-insulator (ETSOI) semiconductor substrates can be improved by forming the source/drain (S/D) regions by in-situ doped epitaxy processing rather than by implant processes.
However, to impart compressive strain to the pFET channel and tensile strain to the nFET channel, such as by forming in-situ boron doped (ISBD) SiGe for the pFET S/D and in-situ phosphorus doped (ISPD) Si for the nFET S/D requires separate epi steps and that presents a number of challenges. One current flow scheme to form a complimentary pair of finFETs, meaning an n-type and p-type pair of finFETs, is illustrated by the path of FIG. 1 which passes through odd numbered steps. The method is applied to an initial structure that includes fins defined on a substrate (104) and a gate stack is formed across the fins (106). A spacer material such as silicon nitride can be deposited as a conformal layer over the gate and fins. A photoresist layer can be patterned (109) to form a soft mask cover over the nFET region and expose the pFET region. (Although this example forms the pFET first, the order can be switched to form the nFET first.) A first directional etch (111), such as nitride RIE, to remove the exposed spacer layer (of 108) from the pFET S/D region exposes the pFET fins and forms the pFET gate spacer. After stripping (113) the soft mask, the pFET S/D can be formed (115) by epitaxial ISBD SiGe growth from the exposed pFET fins. The pFET can then be covered by depositing (116) a hard mask material, such as a second silicon nitride layer. A second photoresist layer can be patterned (118) to form a second soft mask covering the pFET region and exposing the nFET region which at this point includes the layer of step 108 and the layer of step 116. A second etch (119), such as nitride RIE, can remove both layers from the nFET S/D region to expose the nFET fins and forms the nFET gate spacer. After stripping (121) the second soft mask, the nFET S/D can be formed (124) by epitaxial ISPD Si growth from the exposed nFET fins.
However, the dual in-situ doped epitaxy flow described above leads to several problems. For example, the gate spacer in the second to be formed FET is formed from two hard mask layers which may result in that second-formed gate spacer being thicker than the gate spacer of the first formed FET (which is formed from just one hard mask layer). Another problem is that the drive-in anneal to activate the extension requires higher temperature for the pFET than for the nFET. Extension refers to the semiconductor region between source/drain and channel region. In the finFET structure, the extension can include the portion of a fin that is under the gate spacer.
Accordingly, the first formed FET must undergo both anneals which broadens the dopant front at the extension junction which is deleterious to short-channel control. Yet another problem is that the overlay of the first (109) and second (118) lithography can leave a double thickness ridge of hard mask (e.g., spacer) material over the gate at the transition between an adjacent nFET and pFET pair.
There is a need for a CMOS finFET integration scheme that overcomes the above-noted deficiencies.